SN74LVC138ADBR Datasheet PDF - TI

●The SN74LVC138ADBR is a 3-to-8 Decoder/Demultiplexer designed for 1.65 to 3.6V VCC operation. It is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter.

● 5.8ns at 3.3V Maximum tpd

● Latch-up performance exceeds 250mA per JESD 17

● Green product and no Sb/Br