SN74LVC2G34DRLR Datasheet PDF - TI

●The SN74LVC2G34DRLR is a dual Buffer Gate designed for 1.65 to 5.5V VCC operation. This device performs the Boolean function Y = A in positive logic. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

● IOFF Supports live insertion, partial-power-down mode and back-drive protection

● Can be used as a down translator to translate inputs from 5.5V down to the VCC level

● Latch-up performance exceeds 250mA per JESD 17

● Inputs accept voltages to 5.5V

● 4.1ns at 3.3V Propagation delay (tpd)

● 10µA ICC Low power consumption

● ±24mA Output drive at 3.3 V

● <0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)

● >2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)

● Green product and no Sb/Br