●DESCRIPTION/ORDERING INFORMATION
●The SN74LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
●A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
●OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
●The SN74LVC373A is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
●FEATURES
●• Controlled Baseline
● – One Assembly/Test Site, One Fabrication Site
●• Extended Temperature Performance of –40°C to 125°C and –55°C to 125°C
●• Enhanced Diminishing Manufacturing Sources (DMS) Support
●• Enhanced Product-Change Notification
●• QualificationPedigree (1)
●• ESD Protection Exceeds 2000 V Per
● MIL-STD-883, Method 3015; Exceeds 200 V
● Using Machine Model (C = 200 pF, R = 0)
●• Operates From 2 V to 3.6 V
●• Inputs Accept Voltages to 5.5 V
●• Max tpd of 7.5 ns at 3.3 V
●• Typical VOLP (Output Ground Bounce)
● <0.8 V at VCC = 3.3 V, TA = 25°C
●• Typical VOHV (Output VOH Undershoot)
● >2 V at VCC = 3.3 V, TA = 25°C
●• Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
●• Ioff Supports Partial-Power-Down Mode Operation
Part 3D Model
