●description
●The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE),
●which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters.
●Pin-to-Pin Compatible With the Existing TL16C550B/C
●Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts
●Programmable Auto-RTSand Auto-CTS
●In Auto-CTSMode, CTS Controls Transmitter
●In Auto-RTSMode, Receiver FIFO Contents and Threshold Control RTS
●Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop
●Capable of Running With All Existing TL16C450 Software
●After Reset, All Registers Are Identical to the TL16C450 Register Set
●Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation
●In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
●Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216
●–1) and Generates an Internal 16 × Clock
●Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream
●5-V and 3-V Operation
●Register Selectable Sleep Mode and Low-Power Mode
●Independent Receiver Clock Input
●Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts
●Fully Programmable Serial Interface Characteristics:
●– 5-, 6-, 7-, or 8-Bit Characters
●– Even-, Odd-, or No-Parity Bit Generation and Detection
●– 1-, 1 1/2-, or 2-Stop Bit Generation
●– Baud Generation (DC to 1 Mbits Per Second)
●False Start Bit Detection
Part 3D Model
