●Description
●The TLK3134 is a flexible four-channel independently configurable serial transceiver. It can be configured
●to be compliant with the 10Gbps Ethernet XAUI specification. It can also be configured to be compliant
●with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). The TLK3134
●provides high-speed bidirectional point-to-point data transmissions with up to 30 Gbps of raw data
●transmission capacity. The primary application of this device is in backplanes and front panel connections
●requiring 10Gbps connections over controlled impedance media of approximately 50Ω. The transmission
●media can be printed circuit board (PCB) traces, copper cables or fiber-optical media.
● Introduction
●Features
●• Four-Channel 600Mbps to 3.75Gbps Multi-Rate Transceiver
●• Supports 10GbE (XAUI), 1X/2X/10X Fibre Channel (FC), CPRI (x1/x2/x4), OBSAI (x1/x2/x4), and 1GbE (1000Base-X) Data Rates
●• Complete IEEE Compliant 10 GbE XGXS (XAUI) Compliant Core and 1000Base-X PCS Support
●• Supports Independent Channel SERDES Operation Modes in 8/10 Bit Data Modes (TBI and 8 Bit + Control)
●• Serial Side Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended
●Backplane Reach
●• Low Jitter LC Oscillator Jitter-Cleaner Allows use of Poor Quality REFCLK
●• Full Datapath Loopback Capability (Serial/Parallel Side)
●• Support PRBS 27-1 and 223- 1 Gen/Verify. Support standard defined CJPAT, CRPAT, High and Low Frequency, and Mixed Freq Testing.
●• XGMII/GMII/RGMII: HSTL Class 1 I/O With On-Chip 50Ω Termination on Inputs/Outputs (1.5/1.8 V Power Supply)
●• XGMII/GMII/RGMII: Source And Data Centered I/O Timing Modes
●• Supports Jumbo Packet (9600 byte maximum) Operation.
●• XAUI Align Character Skew Support of 30 Bit Times at Chip Pins
●• MDIO: IEEE 802.3ae Clause 22 and Clause 45 Compliant Management Data Input / Output Interface Modes (Either 1.2 V or 2.5 V MDIO I/O)
●• 1.2 V Core, 1.5 V/1.8 V HSTL I/O Supply, and 2.5 V LVCMOS I/O Supply
●• JTAG: IEEE 1149.1/1149.6 Test Interface
●• ±200 ppm Clock Tolerance in XAUI TX and 1000Base-X/XAUI RX Datapaths
●• 90 nm Advanced CMOS Technology
●• Package: PBGA, 19×19mm, 289 Ball, 1mm Pitch
●• 1.3W Maximum Power Dissipation (1.5 V HSTL XAUI Mode, Input HSTL Termination Disabled)
●• Asymmetric RX/TX Rates Supported in Independent Channel Modes
●• Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
●Applications
●• Gigabit Ethernet links
●• CPRI/OBSAI Links
●• Point-to-Point High-Speed Backplane Links
Part 3D Model
