●Description
●The device is a member of TI"s TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family
●and is designed for low-power applications.
●Fixed-Point Digital Signal Processor
●Features
●• High-Performance, Low-Power, TMS320C55x™ • Universal Asynchronous Receiver/Transmitter
●Fixed-Point Digital Signal Processor (UART)
●– 16.67-, 13.33-, 10-, 8.33-ns Instruction Cycle • Serial-Port Interface (SPI) With Four ChipTime Selects
●– 60-, 75-, 100-, 120-MHz Clock Rate • Master/Slave Inter-Integrated Circuit (I2C Bus™)
●– One/Two Instructions Executed per Cycle • Four Inter-IC Sound (I2S Bus™) for Data
●Transport
●– Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)] • Device USB Port With Integrated 2.0 HighSpeed PHY that Supports:
●– Two Arithmetic/Logic Units (ALUs)
●– USB 2.0 Full- and High-Speed Device – Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses • LCD Bridge With Asynchronous Interface
●– Software-Compatible With C55x Devices • Tightly-Coupled FFT Hardware Accelerator
●– Industrial Temperature Devices Available • 10-Bit 4-Input Successive Approximation (SAR) ADC
●• 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
●• Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
●– 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
●• Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB – 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
●• Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DV DDIO
●• 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit) • Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains:
●• 4M x 16-Bit Maximum Addressable External DSP Core, Analog, and USB Core, respectively Memory Space (SDRAM/mSDRAM)
●• Low-Power S/W Programmable Phase-Locked
●• 16-/8-Bit External Memory Interface (EMIF) with Loop (PLL) Clock Generator Glueless Interface to:
●• On-Chip ROM Bootloader (RBL) to Boot From
●– 8-/16-Bit NAND Flash, 1- and 4-Bit ECC NAND Flash, NOR Flash, SPI EEPROM, SPI
●– 8-/16-Bit NOR Flash Serial Flash or I2C EEPROM
●– Asynchronous Static RAM (SRAM)
●• IEEE-1149.1 (JTAG)
●– SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V) Boundary-Scan-Compatible
●• Direct Memory Access (DMA) Controller
●• Up to 26 General-Purpose I/O (GPIO) Pins
●– Four DMA With 4 Channels Each (16-(Multiplexed With Other Device Functions) Channels Total)
●• 196-Terminal Pb-Free Plastic BGA (Ball Grid
●• Three 32-Bit General-Purpose Timers Array) (ZCH Suffix)
●– One Selectable as a Watchdog and/or GP
●• 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V,
●• Two MultiMedia Card/Secure Digital (MMC/SD) or 3.3-V I/Os Interfaces
●• 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
●Applications
●• Wireless Audio Devices (Headsets, Microphones, Speakerphones)
●• Echo Cancellation Headphones
●• Portable Medical Devices
●• Voice Applications
●• Industrial Controls
●• Fingerprint Biometrics
●• Software Defined Radio
Part 3D Model
