TMS320C5515AZCHA12 Datasheet PDF - TI

●The TMS320C5515AZCHA12 is a Digital Signal Processor (DSP) designed for low-power applications. The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

● Low-power S/W programmable phase-locked loop (PLL) clock generator

● Four core isolated power supply domains

● LCD Bridge with asynchronous interface

● Tightly-coupled FFT hardware accelerator

● 10-bit 4-Input successive approximation (SAR) ADC

● Real-time clock (RTC) with crystal input, with separate clock domain and power supply

● Two multimedia card/secure digital (MMC/SD) interfaces

● Universal asynchronous receiver/transmitter (UART)

● Serial-port interface (SPI) with four chip-selects

● Master/slave inter-integrated circuit (I²C Bus™)

● Four inter-IC sound (I²S Bus™) for data transport

● Three internal data/operand read buses and two internal data/operand write buses

● High-performance, low-power, TMS320C55x™ fixed-point digital signal processor

● Green product and no Sb/Br