●The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.
●The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).
●The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.
● Key Features
● High-Performance Multicore DSP (C6474)
● Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
● Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
● Commercial Temperature and Extended Tmperature
● 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
● Enhanced VCP2/TCP2
● Frame Synchronization Interface
● 16-/32-Bit DDR2-667 Memory Controller
● EDMA3 Controller
● Antenna Interface
● Two 1x Serial RapidIO® Links, v1.2 Compliant
● One 1.8-V Inter-Integrated Circuit (I2C) Bus
● Two 1.8-V McBSPs
● 1000 Mbps Ethernet MAC (EMAC)
● Six 64-Bit General-Purpose Timers
● 16 General-Purpose I/O (GPIO) Pins
● Internal Semaphore Module non-UMTS Systems
● System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
● High-Performance Multicore DSP (C6474)
● Instruction Cycle Time:
● 1.2-GHz Device: 1.0-ns to 0.83-ns
● 1-GHz Device: 1-ns
● 850-MHz Device: 1.18 ns
● Clock Rate:
● 1.2-GHz Device: 1-GHz to 1.2-GHz
● 1-GHz Device: 1-GHz
● 850-MHz Device: 850 MHz
● Eight 32-Bit Instructions/Cycle
● Commercial Temperature:
● 1.2-GHz Device: 0°C to 95°C
● 1-GHz Device: 0°C to 100°C
● 850-MHZ and 1-GHz Device: 0°C to 100°C
● Extended Temperature:
● 1.2-GHz Device: -40°C to 95°C(1)
● 1-GHz Device: -40°C to 100°C
● 3 TMS320C64x+™ DSP Cores
● Dedicated SPLOOP Instructions
● Compact Instructions (16-Bit)
● Exception Handling
● TMS320C64x+ Megamodule L1/L2 Memory Architecture
● 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
● 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
● 512 K-Bit (64 K-Byte) L3 ROM
● Enhanced VCP2
● Supports Over 694 7.95-Kbps AMR
● Enhanced Turbo Decoder Coprocessor (TCP2)
● Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
● Endianness: Little Endian, Big Endian
● Frame Synchronization Interface
● Time Alignment Between Internal Subsystems, External Devices/System
● OBSAI RP1 Compliant for Frame Burst Data
● Alternate Interfaces for non-RP1 and non-UMTS Systems
● 16-/32-Bit DDR2-667 Memory Controller
● EDMA3 Controller (64 Independent Channels)
● Antenna Interface
● 6 Configurable Links (Full Duplex)
● Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
● Supports CPRI Protocol V2.0:614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
● Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
● Two 1x Serial RapidIO® Links, v1.2 Compliant
● 1.25-, 2.5-, 3.125-Gbps Link Rates
● Message Passing and DirectIO Support
● Error Management Extensions and Congestion Control
● One 1.8-V Inter-Integrated Circuit (I2C) Bus
● Two 1.8-V McBSPs
● 1000 Mbps Ethernet MAC (EMAC)
● IEEE 802.3 Compliant
● Supports SGMII, v1.8 Compliant
● 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
● Six 64-Bit General-Purpose Timers
● Configurable up to Twelve 32-Bit Timers
● Configurable in a Watchdog Timer mode
● 16 General-Purpose I/O (GPIO) Pins
● Internal Semaphore Module
● Software Method to Control Access to Shared Resources
● 32 General Purpose Semaphore Resources
● System PLL and PLL Controller
● DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
● IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
● 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
● 0.065-µm/7-Level Cu Metal Process (CMOS)
● SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
● 1.8-V, 1.1-V I/Os
●(1)
●Note:
● Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.
●All trademarks are the property of their respective owners.
