TPS3613-01DGS Datasheet PDF - TI

●The TPS3613-01DGS is a Supervisory Circuit with active-low open-drain output. The supervisory circuit monitors and controls processor activity by providing backup-battery switchover for data retention of CMOS RAM. During power-on, reset (RESET and /RESET) is asserted when the supply voltage (VDD or VBAT) becomes higher than 1.1V. Thereafter, the supply voltage supervisor monitors VDD at the SENSE pin through external feedback resistors and keeps reset active as long as SENSE remains below the threshold voltage, VIT. An internal timer delays the release of the reset state to ensure proper system reset. The delay time starts after SENSE rises above the threshold voltage, VIT. When SENSE drops below VIT, reset becomes active again.

● Backup-battery voltage can exceed VDD

● power-ON reset generator

● Active-high and active-low reset output

● Chip-enable gating - 3ns (at VDD=5V) Maximum propagation delay

● Manual reset

● 40µA Maximum supply current

● 100nA Maximum battery supply current

● Green product and no Sb/Br