TPS51206DSQR Datasheet PDF - TI

●The TPS51206 is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The TPS51206 maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The TPS51206 supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk).

●The TPS51206 is available in 10-pin, 2 × 2, SON (DSQ) PowerPAD™ package and specified from –40°C to 85°C.