TPS7350QD Datasheet PDF - TI

●The TPS7350QD is a 5V fixed output low-dropout (LDO) Linear Regulator with integrated delay reset function. The RESET\ output of the device initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the device monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. If that occurs, the RESET\ output turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200ms time-out begins. At the completion of the 200ms delay, RESET\ goes high. An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical PNP pass transistor with a PMOS device. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low and is directly proportional to the output current.

● Integrated precision supply-voltage supervisor monitoring regulator output voltage

● Active-low reset signal with 200ms pulse width

● 340µA Low quiescent current independent of load

● 0.5µA Extremely low sleep-state current

● 2% Tolerance over full range of load, line and temperature

● Very low dropout voltage 35mV at IO - 100mA

● Green product and no Sb/Br