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EP2C8Q208 Datasheet PDF

Part Series:
EP2C8Q208 Series
Category:
FPGAs
Description:
FPGA Cyclone II Family 8256 Cells 402.58MHz 90nm Technology 1.2V 208Pin PQFP
Updated Time: 2023/09/27 08:42:43 (UTC + 8)

EP2C8Q208 Datasheet PDF FPGAs

168 Pages
Altera
FPGA Cyclone II Family 8256 Cells 402.58MHz 90nm Technology 1.2V 208Pin PQFP
168 Pages
Altera
FPGA Cyclone II Family 8256 Cells 402.58MHz 90nm Technology 1.2V 208Pin PQFP

EP2C8Q208C8N - Altera Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
402.58 MHz
Number of Pins
208 Pin
Supply Voltage (DC)
3.30 V
Case/Package
QFP-208
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EP2C8Q208C8N - Altera Function Overview

The EP2C8Q208C8N is a Cyclone® II FPGA with an extend density of 8256 logic elements (LEs) and provide up to 182 usable I/O pins and up to 1.1Mb of embedded memory. Cyclone II FPGA is manufactured on 300mm wafers using TSMC"s 90nm low-k dielectric process to ensure rapid availability and low cost. By minimizing silicon area, Cyclone II devices can support complex digital systems on a single chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who compromise power consumption and performance for low-cost, Altera"s latest generation of low-cost FPGAs-Cyclone II FPGA, offers 60 percent higher performance and half the power consumption of competing 90nm FPGA. It contains a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between logic array blocks (LABs), embedded memory blocks and embedded multipliers.
Embedded multipliers
Advanced I/O support
Flexible clock management circuitry
Altera megafunction and Altera MegaCore function support
Altera Megafunctions Partners Program (AMPPSM) megafunction support
Programmable bus-hold feature
Programmable output drive strength feature
Programmable delays from the pin to the IOE or logic array
Tri-state with weak pull-up on I/O pins before and during configuration
Programmable open-drain outputs
Series on-chip termination support
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