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LAN9220 Datasheet PDF

Part Series:
LAN9220 Series
Category:
Interface ICs
Description:
Ethernet CTLR Single Chip 10Mbps/100Mbps 1.8V/3.3V 56Pin QFN EP
Updated Time: 2023/01/13 03:24:56 (UTC + 8)

LAN9220 Interface ICs Datasheet PDF

LAN9220-ABZJ - Microchip Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
56 Pin
Supply Voltage (DC)
1.62V (min)
Case/Package
QFN-56
Number of Positions
56 Position
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LAN9220-ABZJ - Microchip Function Overview

The LAN9220-ABZJ is a 16-bit Non-PCI small form factor 10/100 Ethernet Controller with variable voltage I/O and HP Auto-MDIX support. It is fully IEEE 802.3 10Base-T and 802.3u 100Base-TX compliant and supports HP Auto-MDIX. The variable voltage I/O signals of the LAN9220 accommodate lower voltage I/O signalling without the need for voltage level shifters. It includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus. The integrated checksum offload engines enable the automatic generation of the 16-bit checksum for received and transmitted Ethernet frames, offloading the task from the CPU. It also includes large transmit and receive data FIFOs to accommodate high latency applications. It supports features which reduce or eliminate packet loss.
Efficient architecture with low CPU overhead
Easily interfaces to most 16-bit embedded CPU"s
Integrated PHY with HP Auto-MDIX support
Integrated checksum offload engine helps reduce CPU load
Low pin count and small body size package for small form factor system designs
Burst-mode read support
Internal buffer memory can store over 200 packets
Automatic PAUSE and back-pressure flow control
Supports Slave-DMA
Interrupt pin with programmable hold-off timer
Reduces system cost and increases design flexibility
SRAM-like interface easily interfaces to most embedded CPU"s or SoC"s
Fully compliant with IEEE 802.3/802.3u standards
Integrated Ethernet MAC and PHY
Full- and half-duplex support
Full-duplex flow control
Backpressure for half-duplex flow control
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Automatic payload padding and pad removal
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