SI5324 Datasheet PDF

● Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz

● Ultra-low jitter clock outputs as low as 290 fs rms (12 kHz–20 MHz), 320 fs rms (50 kHz–80 MHz)

● Integrated loop filter with selectable loop bandwidth (4– 525 Hz)

● Meets ITU-T G.8251 and Telcordia GR-253-CORE jitter specification

● Hitless input clock switching with phase build-out

● Freerun, Digital Hold operation

● Configurable signal format per output (LVPECL, LVDS, CML, CMOS)

● Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236, 239/237, 66/64, 239/238, 15/14, 253/221, 255/238)

● LOL, LOS, FOS alarm outputs

● I2C or SPI programmable

● On-chip voltage regulator with high PSNR

● Single supply 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%

● Small size: 6 x 6 mm 36-lead QFN

● Pb-free, ROHS-compliant