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SN74LVC1T45 Datasheet PDF

Part Series:
SN74LVC1T45 Series
Category:
Voltage Level Translator
Description:
TEXAS INSTRUMENTS SN74LVC1T45DBVR Transceiver, 74LVC1T245, 1.65V to 5.5V, SOT-23-6
Updated Time: 2023/01/13 01:38:37 (UTC + 8)

SN74LVC1T45 Datasheet PDF Voltage Level Translator

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SN74LVC1T45DBVR - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
6 Pin
Supply Voltage (DC)
1.65V ~ 5.50V
Operating Voltage
1.65V ~ 5.5V
Case/Package
SOT-23-6
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SN74LVC1T45DBVR - TI Function Overview

The SN74LVC1T45DBVR is a Single-bit Dual-supply Bus Transceiver with configurable voltage translation and 3-state outputs. This single-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8, 2.5, 3.3 and 5V voltage nodes. Designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
Port to operate over full 1.65 to 5.5V power supply range
VCC isolation feature
DIR input circuit referenced to VCCA
Low power consumption, 4µA maximum ICC
±24mA Output drive at 3.3V
Ioff supports partial power-down mode operation
420, 210, 140 and 75Mbps Maximum data rates
Latch-up performance exceeds 100mA per JESD 78, class II
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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