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T1042 Datasheet PDF

Part Series:
T1042 Series
Category:
Microprocessors
Description:
32Bit, 1200MHz, RISC PROCESSOR, PBGA780
Updated Time: 2023/09/27 08:58:29 (UTC + 8)

T1042 Datasheet PDF Microprocessors

3 Pages
NXP
MPU QorIQ T1042 RISC 64Bit 1.4GHz 780Pin FCBGA Tray
3 Pages
Freescale
IC SOC 4CORE 1200MHz 780FCBGA
3 Pages
NXP
32Bit, 1400MHz, RISC PROCESSOR, PBGA780
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NXP
MPU QorIQ T1042 RISC 64Bit 1.2GHz 780Pin FCBGA Tray
3 Pages
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IC SOC 4CORE 1400MHz 780FCBGA
3 Pages
NXP
MPU QorIQ T1042 RISC 64Bit 1.4GHz 780Pin FCBGA Tray
3 Pages
NXP
MPU QorIQ T RISC 64Bit 1500MHz 780Pin FCP-BGA Box
3 Pages
NXP
QorIQ, 4x e5500, 1500MHz, DDR3L/4, No Crypto, No Switch, 0 to 105
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NXP
MPU QorIQ T RISC 64Bit 1500MHz 780Pin FCP-BGA Box

T1042NSN7MQB - NXP Specifications

TYPE
DESCRIPTION
Frequency
1200 MHz
Number of Pins
780 Pin
Case/Package
FCBGA-780
Operating Temperature (Max)
105 ℃
Operating Temperature (Min)
0 ℃
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T1042NSN7MQB - NXP Function Overview

Overview
The QorIQ T1042 quad-core and T1022 dual-core communication processors support two or four integrated 64-bit e5500 Power Architecture® processor cores with high-performance data path acceleration architecture (DPAA) and network peripheral interfaces required for networking and telecommunications.
The T1 family of devices is one of the industry’s most scalable, pin-compatible family of communications processors – and offers pin-compatible migration up to the higher-performance QorIQ T2081 device.
MoreLess
## Features
### Core Complex
Two or four e5500 cores, built on Power Architecture technology
Up to 1.4 GHz with 64-bit ISA support
Three levels of instructions: user, supervisor, hypervisor
Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
256 KB backside L2 cache
### Networking Elements
SerDes
Eight lanes at up to 5 Gbps
Supports SGMII, QSGMII, PCIe and SATA
Ethernet Interfaces
Up to five Gigabit Ethernet interfaces
### Accelerators and Memory Control
32/64-bit DDR3L/4 SDRAM memory controller with ECC support
Up to 1600 MT/s
DPAA Incorporating acceleration for the following functions Packet parsing, classification, and distribution
Queue management for scheduling, packet sequencing and congestion management
Hardware buffer management for buffer allocation and de-allocation
Integrated security acceleration (SEC)
Signature detection (PME)
### Basic Peripherals and Interconnect
CoreNet® platform cache
256 KB shared platform cache
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
Additional peripheral interfaces two Serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHYs
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I²C controllers
Four UARTS
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Up to 5x 1 Gbps Ethernet MACs as part of DPAA
QUICC Engine®
Support for legacy protocols TDM, HDLC, UART and ISDN
High-speed peripheral interfaces
Four PCI Express® 2.0 controllers
### Additional Features
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ® trust architecture
Secure boot, secure debug, tamper detection, volatile key storage
This product is included in Our product longevity program, with assured supply for a minimum of 10 years after launchComparison Table
| T1020 | T1022 | T1040 | T1042 | T2081
\---|---|---|---|---|---
CPU
| 2 e5500| 2 e5500| 4 e5500| 4 e5500| 4 e6500 (dual-threaded)
Core Frequency
| 1200-1400MHz| 1200-1400MHz| 1200-1400MHz| 1200-1400MHz| 1500-1800MHz
DDR I/F
| 1x DDR3L/4 to 1600MT/s| 1x DDR3L/4 to 1600MT/s| 1x DDR3L/4 to 1600MT/s| 1x DDR3L/4 to 1600MT/s| 1x DDR3/3L to 2133MT/s
Ethernet (with IEEE1588v2)
| 8-Port GE Switch + 4x 1GE| 5x 1GE| 8-Port GE Switch + 4x 1GE| 5x 1GE| 2x 1/10GE + 6x 1GE
SERDES
| 8 lanes (5GHz)| 8 lanes (5GHz)| 8 lanes (5GHz)| 8 lanes (5GHz)| 8 lanes (10GHz)
Package
| Pin Compatible
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