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USB3300 Datasheet PDF

Part Series:
USB3300 Series
Category:
USB Interface Ics
Description:
USB Interface, USB PHY Transceiver, USB 2.0, 3V, 3.6V, QFN, 32Pins
Updated Time: 2023/01/13 01:46:54 (UTC + 8)

USB3300 USB Interface Ics Datasheet PDF

USB3300-EZK - Microchip Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
32 Pin
Supply Voltage (DC)
3.00V (min)
Case/Package
QFN-32
Number of Positions
32 Position
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USB3300-EZK - Microchip Function Overview

The USB3300-EZK is an industrial temperature high-speed USB physical layer transceiver (PHY) IC, uses a low pin count interface (ULPI) to connect to a ULPI compliant link layer. The ULPI interface reduces the UTMI+ interface from 54 to 12 pins using a method of in-band signalling and status byte transfers between the link and PHY. This PHY was designed from the start with the ULPI interface. No UTMI to ULPI wrappers are used in this design which provides a seamless ULPI to Link interface. The result is a PHY with a low latency transmit and receive time. Microchip"s low latency high speed and full speed receiver provide the option of re-using existing UTMI Links with a simple wrapper to convert UTMI to ULPI.
USB-IF High-speed Certified to Universal Serial Bus Specification Rev. 2.0
Interface Compliant with ULPI Specification Revision 1.1 in 8-bit Mode
Industry standard ULPI converts 54 UTMI+ signals into a standard 12-pin link controller Interface
54.7mA Un-configured Current (Typical), Ideal for Bus Powered Applications
83µA Suspend Current (Typical), Ideal for Battery-powered Applications
Latch-up Performance Exceeds 150mA per EIA/JESD 78, Class II
ESD Protection Levels of ±8kV HBM without External Protection Devices
Integrated protection to withstand IEC61000-4-2 ESD tests (±8kV Contact and ±15kV Air)
Supports FS Pre-amble for FS Hubs with a LS Device Attached (UTMI+ Level 3)
Supports HS SOF and LS Keep-alive Pulse
Includes full support for optional On-The-Go Protocol detailed in On-The-Go supplement rev 1.0a spec
Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
Allows Host to Turn VBUS Off to Conserve Battery Power in OTG Applications
Supports OTG Monitoring of VBUS Levels with Internal Comparators
Includes Support for an External VBUS or Fault Monitor
Low Latency High-speed Receiver allows use of legacy UTMI links with a ULPI wrapper
Integrated Pull-up resistor on STP for interface allows a reliable Link/PHY Start-up with SLOW links
Internal 1.8V Regulators Allow Operation from a Single 3.3V Supply
Internal Short-circuit Protection of ID, DP and DM lines to VBUS or Ground
Integrated 24MHz Crystal Oscillator Supports Either Crystal Operation or 24MHz External Clock Input
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