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XC3S200 Datasheet PDF

Part Series:
XC3S200 Series
Category:
FPGAs
Description:
FPGA Spartan-3AN Family 200K Gates 4032 Cells 667MHz 90nm Technology 1.2V 256Pin FTBGA
Updated Time: 2023/01/13 02:37:32 (UTC + 8)

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Field Programmable Gate Array, 448 CLBs, 200000Gates, 280MHz, 4032-Cell, CMOS, PBGA256, 17 X 17MM, ROHS COMPLIANT, FTBGA-256
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FPGA Spartan-3AN 200K Gates 4032 Cells 770MHz 90nm Technology 1.2V 256Pin FCBGA

XC3S200AN-4FTG256C - Xilinx Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
250 MHz
Number of Pins
256 Pin
Case/Package
BGA-256
Number of Positions
256 Position
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XC3S200AN-4FTG256C - Xilinx Function Overview

The XC3S200AN-4FTG256C is a Spartan®-3AN FPGA combines the best attributes of a leading edge, FPGA with non-volatile technology across a broad range of densities. The family combines all the features of the Spartan®-3A FPGA family plus leading technology in-system Flash memory for configuration and non-volatile data storage. It is a part of the extended Spartan-3A family, which also includes the Spartan®-3A FPGA and the higher density Spartan®-3A DSP FPGA. Combining FPGA and Flash technology minimizes chip count, PCB traces and overall size while increasing system reliability. The FPGA internal configuration interface is completely self-contained, increasing design security. The family maintains full support for external configuration. It is the world"s first non-volatile FPGA with MultiBoot, supporting two or more configuration files in one device, allowing alternative configurations for field upgrades, test modes or multiple system configurations.
Eliminates traditional non-volatile FPGA limitations
Integrated robust configuration memory
Plentiful amounts of non-volatile memory available to the user
Robust 100k Flash memory program/erase cycles
20 Years Flash memory data retention
Security features provide bitstream anti-cloning protection
Configuration watchdog timer automatically recovers from configuration errors
Suspend mode reduces system power consumption
Full hot-swap compliance
Multi-voltage, multi-standard SelectIO™ interface pins
Abundant, flexible logic resources
Hierarchical SelectRAM™ memory architecture
Up to eight Digital Clock Managers (DCMs)
Eight global clocks and eight additional clocks per each half of device
Complete Xilinx® ISE® and WebPACK™ software development system support
MicroBlaze™ and PicoBlaze™ embedded processor cores
Fully compliant 32/64-bit 33MHz PCI™ technology support
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