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74HC273 Datasheet PDF

Part Series:
74HC273 Series
Category:
Logic ICs
Description:
IC D-TYPE POS TRG SNGL 20SOIC
Updated Time: 2023/01/13 01:33:40 (UTC + 8)

74HC273 Datasheet PDF Logic ICs

22 Pages
NXP
NXP 74HC273N,652 Flip-Flop, 74HC273, D, 15ns, 122MHz, 5.2mA, DIP
22 Pages
Nexperia
IC D-TYPE POS TRG SNGL 20DHVQFN
22 Pages
Nexperia
Flip Flop D-Type Bus Interface Pos-Edge 1Element 20Pin SO
21 Pages
Nexperia
IC D-TYPE POS TRG SNGL 20SOIC
21 Pages
NXP
NXP 74HC273D Flip-Flop, with Reset, Non Inverted, Positive Edge, 74HC273, D, 13ns, 66MHz, 5.2mA, SOIC
21 Pages
Nexperia
IC D-TYPE POS TRG SNGL 20SOIC
21 Pages
NXP
NXP 74HC273N Flip-Flop, 74HC273, D, 13ns, 66MHz, 5.2mA, DIP
21 Pages
NXP
Flip Flop D-Type Bus Interface Pos-Edge 1Element 20Pin SSOP T/R
21 Pages
NXP
Flip Flop D-Type Bus Interface Pos-Edge 1Element 20Pin TSSOP Tube
21 Pages
Nexperia
IC D-TYPE POS TRG SNGL 20SSOP
21 Pages
NXP
Flip Flop D-Type Bus Interface Pos-Edge 1Element 20Pin TSSOP Tube
21 Pages
NXP
Flip Flop D-Type Bus Interface Pos-Edge 1Element 20Pin DHVQFN EP T/R
21 Pages
Philips
74HC/HCT273; Octal D-type flip-flop with reset; positive-edge trigger
21 Pages
Philips
74HC/HCT273; Octal D-type flip-flop with reset; positive-edge trigger
21 Pages
Toshiba
Flip Flop D-Type Bus Interface Pos-Edge 1Element 20Pin SOIC
21 Pages
Nexperia
IC D-TYPE POS TRG SNGL 20TSSOP

74HC273D,653 - Nexperia Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
122 MHz
Number of Pins
20 Pin
Capacitance
3.5 pF
Case/Package
SOIC-20
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74HC273D,653 - Nexperia Function Overview

The 74HC273D is an octal positive-edge triggered D-type Flip-flop features clock (CP) and master reset (MR\\) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the low-to-high clock transition. A low on MR\ forces the outputs low independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Common clock and master reset
CMOS Input levels
Complies with JEDEC standard No. 7A
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