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AD9520 Datasheet PDF

Part Series:
AD9520 Series
Category:
Clock & Timing
Description:
ANALOG DEVICES AD9520-4BCPZ Clock Generator, Parallel, Serial, 1.8GHz, 3.135V-3.465V supply, 12Outputs, LFCSP-64
Updated Time: 2023/01/13 03:04:57 (UTC + 8)

AD9520 Datasheet PDF Clock & Timing

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ANALOG DEVICES AD9520-5/PCBZ 12/24Channel CLOCK GEN 2 0GH

AD9520-4BCPZ - ADI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
1.8 GHz
Number of Pins
64 Pin
Supply Voltage (DC)
3.13V (min)
Case/Package
LFCSP-64
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AD9520-4BCPZ - ADI Function Overview

GENERAL DESCRIPTION
The AD9520-41 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.4 GHz to 1.8 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.
The AD9520 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register setting for power-up and chip reset.
The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs.
FEATURES
  Low phase noise, phase-locked loop (PLL)
     On-chip VCO tunes from 1.4 GHz to 1.8 GHz
     Supports external 0 V to 5 V VCO/VCXO to 2.4 GHz
     1 differential or 2 single-ended reference inputs
     Accepts CMOS, LVDS, or LVPECL references to 250 MHz
     Accepts 16.67 MHz to 33.3 MHz crystal for reference input
     Optional reference clock doubler
     Reference monitoring capability
     Auto and manual reference switchover/holdover modes,
     with selectable revertive/nonrevertive switching
     Glitch-free switchover between references
     Automatic recover from holdover
     Digital or analog lock detect, selectable
     Optional zero delay operation
  Twelve 1.6 GHz LVPECL outputs divided into 4 groups
     Each group of 4 has a 1-to-32 divider with phase delay
     Additive output jitter as low as 225 fS rms
     Channel-to-channel skew grouped outputs <16 ps
     Each LVPECL output can be configured as two CMOS outputs (for fOUT ≤ 250 MHz)
  Automatic synchronization of all outputs on power-up
  Manual synchronization of outputs as needed
  SPI- and I²C-compatible serial control port
  64-lead LFCSP
  Nonvolatile EEPROM stores configuration settings
  APPLICATIONS
  Low jitter, low phase noise clock distribution
  Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
  Forward error correction (G.710)
  Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
  High performance wireless transceivers
  ATE and high performance instrumentation
  Broadband infrastructures
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