74LVC1G80GW Datasheet PDF - NXP

●General description

●The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop.

●Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

●Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

●Features

●■ Wide supply voltage range from 1.65 V to 5.5 V

●■ High noise immunity

●■ Complies with JEDEC standard:

●   ◆ JESD8-7 (1.65 V to 1.95 V)

●   ◆ JESD8-5 (2.3 V to 2.7 V)

●   ◆ JESD8B/JESD36 (2.7 V to 3.6 V)

●■ ±24 mA output drive (VCC = 3.0 V)

●■ CMOS low power consumption

●■ Latch-up performance exceeds 250 mA

●■ Direct interface with TTL levels

●■ Inputs accept voltages up to 5 V

●■ Multiple package options

●■ ESD protection:

●   ◆ HBM JESD22-A114E exceeds 2000 V

●   ◆ MM JESD22-A115-A exceeds 200 V

●■ Specified from −40 °C to +125 °C