●GENERAL DESCRIPTION
●The AD9516-01 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz may be used.
●The AD9516-0 emphasizes low jitter and phase noise to maximize data converter performance, and can benefit other applications with demanding phase noise and jitter requirements.
●The AD9516-0 features six LVPECL outputs (in three pairs); four LVDS outputs (in two pairs); and eight CMOS outputs (two per LVDS output). The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz
●FEATURES
● Low phase noise, phase-locked loop
● On-chip VCO tunes from 2.55 GHz to 2.95 GHz
● External VCO/VCXO to 2.4 GHz optional
● One differential or two single-ended reference inputs
● Reference monitoring capability
● Auto and manual reference switchover/holdover modes
● Autorecover from holdover
● Accepts references to 250 MHz
● Programmable delays in path to PFD
● Digital or analog lock detect, selectable
● 3 pairs of 1.6 GHz LVPECL outputs
● Each pair shares 1 to 32 divider with coarse phase delay
● Additive output jitter 225 fS rms
● Channel-to-channel skew paired outputs <10 ps
● 2 pairs of 800 MHz LVDS clock outputs
● Each pair shares two cascaded 1 to 32 dividers with coarse phase delay
● Additive output jitter 275 fS rms
● Fine delay adjust (ΔT) on each LVDS output
● Eight 250 MHz CMOS outputs (two per LVDS output)
● Automatic synchronization of all outputs on power-up
● Manual synchronization of outputs as needed
● Serial control port
● 64-lead LFCSP
●APPLICATIONS
● Low jitter, low phase noise clock distribution
● Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
● High performance wireless transceivers
● High performance instrumentation
● Broadband infrastructure
● ATE
Part 3D Model
