●Product Details
●The AD9516-51 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO/VCXO of up to 2.4 GHz.
●The AD9516-5 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.
●The AD9516-5 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
●Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.
●The AD9516-5 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V (nominal).
●The AD9516-5 is specified for operation over the industrial range of −40°C to +85°C.
●For applications requiring an integrated EEPROM, or needing additional outputs, the AD9520-5 and AD9522-5 are available.
●Applications
● Low jitter, low phase noise clock distribution
● 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
● Forward error correction (G.710)
● Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
● High performance wireless transceivers
● ATE and high performance instrumentation
●1 AD9516 is used throughout the data sheet to refer to all members of the AD9516 family. However, when AD9516-5 is used, it refers to that specific member of the AD9516 family.
●### Features and Benefits
● Low phase noise, phase-locked loop
●(Please see data sheet for additional details)
● Six 1.6 GHz LVPECL outputs arranged in 3 groups (Please see data sheet for additional details)
● Four 800 MHz LVDS clock outputs arranged in 2 groups
●Each group shares 2 cascaded 1-to-32 dividers with coarse phase delay
● Automatic synchronization of all outputs on power-up
● Manual output synchronization available
● Available in 64-lead LFCSP
Part 3D Model
