●Product Details
●The ADN4690E/ADN4692E/ADN4694E/ADN4695E are multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 100 Mbps (50 MHz). Slew rate control is implemented on the driver outputs. The receivers detect the bus state with a differential input of as little as 50 mV over a common-mode voltage range of −1 V to +3.4 V. ESD protection of up to ±15 kV is implemented on the bus pins. The parts adhere to the TIA/EIA-899 standard for M-LVDS and complement TIA/EIA-644 LVDS devices with additional multipoint capabilities.
●The ADN4690E/ADN4692E are Type 1 receivers with 25 mV of hysteresis, so that slow-changing signals or loss of input does not lead to output oscillations. The ADN4694E/ADN4695E are Type 2 receivers exhibiting an offset threshold, guaranteeing the output state when the bus is idle (bus-idle fail-safe) or the inputs are open (open-circuit fail-safe).
●The parts are available as half-duplex in an 8-lead SOIC package (the ADN4690E/ADN4694E) or as full-duplex in a 14-lead SOIC package (the ADN4692E/ADN4695E).
●Applications
● Backplane and cable multipoint data transmission
● Multipoint clock distribution
● Low power, high speed alternative to shorter RS-485 links
● Networking and wireless base station infrastructure
●### Features and Benefits
● Multipoint LVDS transceivers (low voltage differential signaling driver and receiver pairs)
● Switching rate: 100 Mbps (50 MHz)
● Supported bus loads: 30 Ω to 55 Ω
● Choice of 2 receiver types
● Type 2 (ADN4694E/ADN4695E): threshold offset of 100 mV for open-circuit and bus-idle fail-safe
● Conforms to TIA/EIA-899 standard for M-LVDS
● Glitch-free power-up/power-down on M-LVDS bus
● Controlled transition times on driver output
● Common-mode range: −1 V to +3.4 V, allowing communication with 2 V of ground noise
● See data sheet for additional features
Part 3D Model
