● 375- and 456-MHzARM926EJ-S RISC MPU
● ARM926EJ-S Core
● 32-Bit and 16-Bit (Thumb) Instructions
● Single-Cycle MAC
● ARM Jazelle Technology
● Embedded ICE-RT for Real-Time Debug
● ARM9 Memory Architecture
● 16KB of Instruction Cache
● 16KB of Data Cache
● 8KB of RAM (Vector Table)
● 64KB of ROM
● Enhanced Direct Memory Access Controller 3(EDMA3):
● 2 Channel Controllers
● 3 Transfer Controllers
● 64 Independent DMA Channels
● 16 Quick DMA Channels
● Programmable Transfer Burst Size
● 128KB of On-Chip Memory
● 1.8-V or 3.3-V LVCMOS I/Os (Exceptfor USB and DDR2 Interfaces)
● Two External Memory Interfaces:
● EMIFA
● NOR (8- or 16-Bit-Wide Data)
● NAND (8- or 16-Bit-Wide Data)
● 16-Bit SDRAM with 128-MB Address Space
● DDR2/Mobile DDR Memory Controller with one of the following:
● 16-Bit DDR2 SDRAM with 256-MB Address Space
● 16-Bit mDDR SDRAM with 256-MB Address Space
● Three Configurable 16550-Type UART Modules:
● With Modem Control Signals
● 16-Byte FIFO
● 16x or 13x Oversampling Option
● LCD Controller
● Two Serial Peripheral Interfaces (SPIs) Each with Multiple ChipSelects
● Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure DataI/O (SDIO) Interfaces
● Two Master and Slave Inter-Integrated Circuits (I2C Bus)
● One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus ForHigh Bandwidth
● Programmable Real-Time Unit Subsystem (PRUSS)
● Two Independent Programmable Real-Time Unit (PRU) Cores
● 32-Bit Load-Store RISC Architecture
● 4KB of Instruction RAM per Core
● 512 Bytes of Data RAM per Core
● PRUSS can be Disabled via Software to Save Power
● Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
● Standard Power-Management Mechanism
● Clock Gating
● Entire Subsystem Under a Single PSC Clock Gating Domain
● Dedicated Interrupt Controller
● Dedicated Switched Central Resource
● USB 1.1 OHCI (Host) with Integrated PHY (USB1)
● USB 2.0 OTG Port with Integrated PHY (USB0)
● USB 2.0 High- and Full-Speed Client
● USB 2.0 High-, Full-, and Low-Speed Host
● End Point 0 (Control)
● End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
● One Multichannel Audio Serial Port (McASP):
● Transmit and Receive Clocks
● Two Clock Zones and 16 Serial Data Pins
● Supports TDM, I2S, and Similar Formats
● DIT-Capable
● FIFO Buffers for Transmit and Receive
● Two Multichannel Buffered Serial Ports (McBSPs):
● Transmit and Receive Clocks
● Supports TDM, I2S, and Similar Formats
● AC97 Audio Codec Interface
● Telecom Interfaces (ST-Bus, H100)
● 128-Channel TDM
● FIFO Buffers for Transmit and Receive
● 10/100 Mbps Ethernet MAC (EMAC):
● IEEE 802.3 Compliant
● MII Media-Independent Interface
● RMII Reduced Media-Independent Interface
● Management Data I/O (MDIO) Module
Part 3D Model
