●GENERAL DESCRIPTION
●The Am29LV040B is a single power supply, 4 Mbit, 3.0 Volt-only Flash memory device organized as 524,288 bytes. The data appears on DQ0-DQ7. The device is available in 32-pin PLCC and 32-pin TSOP packages. All read, erase, and program operations are accomplished using only a single power supply.
●The device can also be programmed in standard EPROM programmers. The device offers access times of 60, 70, 90, and 120 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—to control normal read and write operations.
●The device requires only a single power supply(2.7V–3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
●The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from ther
●Flash or EPROM devices.
●DISTINCTIVE CHARACTERISTICS
●■Single power supply operation
●— Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
●— Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors
●■Manufactured on 0.32 µm process technology
●■High performance
●— Full voltage range: access times as fast as 70 ns
●— Regulated voltage range: access times as fast as 60 ns
●■Ultra low power consumption (typical values at 5MHz)
●— Automatic sleep mode: 0.2 µA
●— Standby mode: 0.2 µA
●— Read mode: 7 mA
●— Program/erase mode: 15 mA
●■Flexible sector architecture
●— Eight 64 Kbyte sectors
●— Any combination of sectors can be erased;
●supports full chip erase
●— Sector Protection features: Hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment
●■Unlock Bypass Program Command
●— Reduces overall programming time when issuing multiple program command sequences
●■Embedded Algorithms
●— Embedded Erase algorithms automatically preprogram and erase the entire chip or any
●combination of designated sectors
●— Embedded Program algorithms automatically writes and verifies data at specified addresses
●■Minimum 1,000,000 erase cycles guaranteed
●■20-year data retention at 125°C
●— Reliable operation for the life of the system
●■Package option
●— 32-pin PLCC
●— 32-pin TSOP
●■Compatibility with JEDEC standards
●— Pinout and software compatible with single power supply Flash
●— Superior inadvertent write protection
●■Data# Polling and toggle bits
●— Provides a software method of detecting program or erase cycle completion
●■Erase Suspend/Resume
●— Supports reading data from or programming data to a sector not being erased
Part 3D Model
