EP1C3T100C8N Datasheet PDF - Altera

●The EP1C3T100C8N is a surface mount Field Programmable Gate Array IC with PLL clock management and 2910 logic elements. The Cyclone™ field programmable gate array with features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements. It support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

● Up to 294912 RAM bits

● Support for LVTTL, LVCMOS, SSTL-2 and SSTL-3 I/O standards

● High-speed (640Mbps) LVDS I/O support

● Low-speed (311Mbps) LVDS I/O support

● 311Mbps RSDS I/O support