● Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single device
● Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
● Dual-port capability with up to 16-bit width per embedded array block (EAB)
● Logic array for general logic functions
● High density
● 100,000 typical gates
● Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity)
● Cost-efficient programmable architecture for high Volume applications
● Cost-optimized process
● Low cost solution for high-performance communications applications
● System-level features
● MultiVoltTM I/O pins can drive or be driven by 2.5 V, 3.3 V, or 5.0 V devices
● Low power consumption
● Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz
● Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3 V operation at 33 MHz or 66 MHz
● Extended temperature range
● -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2 for 5.0 V operation
● Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic.
● Operate with a 2.5 V internal supply voltage
● In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port
● ClockLockTM and ClockBoostTM options for reduced clock delay, clock skew, and clock multiplication
● Built-in, low-skew clock distribution trees
● 100% functional testing of all devices; test vectors or scan chains are not required
● Pull-up on I/O pins before and during configuration
Part 3D Model
