GS816032BGT-150IV Datasheet PDF - Giga Semiconductor

●Functional Description

●Applications

●The GS8160xxBT-xxxV is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

●Features

●• FT pin for user-configurable flow through or pipeline operation

●• Single Cycle Deselect (SCD) operation

●• 1.8 V or 2.5 V core power supply

●• 1.8 V or 2.5 V I/O supply

●• LBO pin for Linear or Interleaved Burst mode

●• Internal input resistors on mode pins allow floating mode pins

●• Default to Interleaved Pipeline mode

●• Byte Write (BW) and/or Global Write (GW) operation

●• Internal self-timed write cycle

●• Automatic power-down for portable applications

●• JEDEC-standard 100-lead TQFP package

●• RoHS-compliant 100-lead TQFP package available