● Main Cortex-M4 processor:
● ARM Cortex-M4 processor, running at frequencies of up to 204 MHz
● ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions
● ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
● Hardware floating-point unit
● Non-maskable Interrupt (NMI) input
● JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watchpoints
● Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support
● System tick timer
● Cortex-M0 coprocessor:
● ARM Cortex-M0 coprocessor capable of off-loading the main ARM Cortex-M4processor
● Running at frequencies of up to 204 MHz
● JTAG and built-in NVIC
● Cortex-M0 subsystem:
● ARM Cortex-M0 processor controlling the SPI and SGPIO peripherals residing ona separate AHB multilayer matrix with direct access to 2 kB + 16 kB of SRAM
● Running at frequencies of up to 204 MHz
● Connected via a core-to-core bridge to the main AHB multilayer matrix and themain ARM Cortex-M4 processor
● JTAG and built-in NVIC
● On-chip memory:
● 264 kB SRAM for code and data use on the main AHB multilayer matrix plus 18 kBof SRAM on the Cortex-M0 subsystem
● Multiple SRAM blocks with separate bus access. Two SRAM blocks can bepowered down individually
● 64 kB ROM containing boot code and on-chip software drivers
● 64-bit + 256 bit general-purpose One-Time Programmable (OTP) memory
● Configurable digital peripherals:
● Serial GPIO (SGPIO) interface
● State Configurable Timer (SCT) subsystem on AHB
● Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs andoutputs to event driven peripherals like the timers, SCT, and ADC0/1
● Serial interfaces:
● Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second
● 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for highthroughput at low CPU load. Support for IEEE 1588 time stamping/advanced timestamping (IEEE 1588-2008 v2)
● One High-speed USB 2.0 Host/Device/OTG interface with DMA support andon-chip high-speed PHY
● One High-speed USB 2.0 Host/Device interface with DMA support, on-chipfull-speed PHY and ULPI interface to external high-speed PHY
● USB interface electrical test software included in ROM USB stack
● One 550 UART with DMA support and full modem interface
● Three 550 USARTs with DMA and synchronous mode support and a smart cardinterface conforming to ISO7816 specification. One USART with IrDA interface
● Two C_CAN 2.0B controllers with one channel each. Use of C_CAN controllerexcludes operation of all other peripherals connected to the same bus bridge
● Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMAsupport
● One SPI controller
● One Fast-mode Plus I²C-bus interface with monitor mode and open-drain I/Opins conforming to the full I²C-bus specification. Supports data rates of up to1 Mbit/s
● One standard I²C-bus interface with monitor mode and with standard I/O pins
● Two I²S interfaces, each with DMA support and with one input and one output
● Digital peripherals:
● External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,and SDRAM devices
● LCD controller with DMA support and a programmable display resolution of up to1024 H x768 V. Supports monochrome and color STN panels and TFT colorpanels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixelmapping
● Secure Digital Input Output (SD/MMC) card interface
● Eight-channel General-Purpose DMA (GPDMA) controller can access all memorieson the AHB and all DMA-capable AHB slaves
● 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-downresistors and open-drain mode
Part 3D Model
