NB6N11SMNG Datasheet PDF - ON Semiconductor

●The NB6N11SMNG is a 1:2 AnyLevel™ input to LVDS fan-out Buffer/Translator has a wide input common mode range from GND + 50mV to VCC - 50mV. Combined with the 50R internal termination resistors at the inputs, the NB6N11S is ideal for translating a variety of differential or single-ended clock or data signals to 350mV typical LVDS output levels. It is a differential 1:2 clock or data receiver and will accept AnyLevel input signals of LVPECL/CML/LVCMOS/LVTTL/LVDS. These signals will be translated to LVDS and two identical copies of clock or data will be distributed, operating up to 2GHz or 2.5Gb/s respectively. As such, the NB6N11S is ideal for SONET, GigE, fiber channel, backplane and other clock or data distribution applications.

● 1ps Maximum of RMS clock jitter

● Typically 10ps of data dependent jitter

● 380ps Typical propagation delay

● 120ps Typical rise and fall times

● Functionally compatible with existing 3.3V LVEL/LVEP/EP/SG devices