S25FS128SDSNFI101 Datasheet PDF - Cypress Semiconductor

●The S25FS128SDSNFI101 is a 128MB MirrorBit® Flash Non-Volatile Memory with 1.8V single supply and CMOS I/O serial peripheral interface with multi-I/O. Traditional SPI 1-bit serial input and output is supported as well as optional 2-bit and 4-bit wide quad I/O or quad peripheral interface serial commands. This multiple width interface is called SPI multi-I/O or MIO. In addition, there are double data rate read commands for QIO and QPI that transfer address and read data on both edges of the clock. The FS-S eclipse architecture features a page programming buffer that allows up to 512 bytes to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. By using S25FS-S family device at the higher clock rates supported, with quad or DDR quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically.

● SPI Clock polarity and phase modes 0 and 3

● Serial command set and footprint compatible with S25FL-A, S25FL-K and S25FL-P SPI families

● Multi I/O command set and footprint compatible with S25FL-P and S25FL-S SPI family

● Serial flash discoverable parameters and common flash interface, for configuration information

● Program suspend and resume

● Erase suspend and resume

● Erase status evaluation

● 100000 Program-erase cycles on any sector minimum

● 20 Years data retention typical

● Individual sector protection controlled by boot code or password

● Spansion 65nm MirrorBit technology with Eclipse™ Architecture