SN65MLVD2DRBT Datasheet PDF - TI

●DESCRIPTION

●The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled.

●FEATURES

●• Low-Voltage Differential 30-Ω to 55-Ω Line Receivers for Signaling Rates(1) up to 250Mbps; Clock Frequencies up to 125MHz

●• SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis

●• SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions

●• Wide Receiver Input Common-Mode Voltage Range, –1 V to 3.4 V, Allows 2 V of Ground Noise

●• Improved VIT (35 mV)

●• Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology

●• High Input Impedance with Low Supply Voltage

●• Bus-Pin HBM ESD Protection Exceeds 9 kV

●• Packaged in 8-Pin SON (DRB) 70% Smaller Than8-PinSOIC

●APPLICATIONS

●• Parallel Multipoint Data and Clock

●  Transmission via Backplanes and Cables

●• Cellular Base Stations

●• Central Office Switches

●• Network Switches and Routers