SN74AHC138DR Datasheet PDF - TI

●The SN74AHC138DR is a 3-to-8 Decoder/Demultiplexer designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

● Designed specifically for high-speed memory decoders and data-transmission systems

● Incorporate three enable inputs to simplify cascading and/or data reception

● Latch-up performance exceeds 250mA per JESD 17

● Green product and no Sb/Br