SN74HC74QDRQ1 Datasheet PDF - TI

●description/ordering information

●The SN74HC74 device contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PREand CLRare inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

●Qualification in Accordance With AEC-Q100†

● Qualified for Automotive Applications

●Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval

● Wide Operating Voltage Range of 2 V to 6 V

● Outputs Can Drive Up To 10 LSTTL Loads

●Low Power Consumption, 80-µA Max ICC

● Typical tpd = 15 ns

●±4-mA Output Drive at 5 V

● Low Input Current of 1 µA Max