SN74LV273APWR Datasheet PDF - TI

●The SN74LV273APWR is an octal positive-edge-triggered D-type Flip-flop with clear. It is designed for 2 to 5.5V VCC operation. It supports mixed-mode voltage operation on all ports. This device is a positive-edge-triggered flip-flop with direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D-input signal has no effect at the output.

● Latch-up performance exceeds 250mA per JESD 17

● Maximum tpd of 10.5ns at 5V

● Allows down-voltage translation

● Slow edges reduce noise

● Supports mixed-mode voltage operation on all ports