SN74LV8151PW Datasheet PDF - TI

●The SN74LV8151PW is a 10-bit universal Schmitt-Trigger Buffer with 3-state outputs designed for 2 to 5.5V VCC operation. The logic control (T/C\\) pin allows the user to configure Y1 to Y8 as non-inverting or inverting outputs. When T/C\ is high, the Y-outputs are non-inverted (true logic ) and when T/C\ is low, the Y-outputs are inverted (complementary logic). When output-enable (OE)\ input is low, the device passes data from Dn to Yn. When OE\ is high, the Y-outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer and the path B to N is a simple Schmitt-trigger inverter. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

● 15ns at 5V Maximum TPD

● Schmitt-trigger inputs allow for slow input rise or fall time

● Polarity control for Y-outputs selects true or complementary logic

● IOFF supports partial-power-down mode operation

● Supports mixed-mode voltage operation on all ports

● Latch-up performance exceeds 250mA per JESD 17

● ESD protection exceeds JESD 22