SN74LVC16244ADGGR Datasheet PDF - TI

●The SN74LVC16244ADGGR is a 16-bit Buffer/Driver with 3-state outputs. This device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers and bus-oriented receivers and transmitters. It can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device provides true outputs and symmetrical active-low output-enable (OE) inputs. Inputs can be driven from either 3.3/5V devices. This feature allows the use of this device as a translator in a mixed 3.3 and 5V system environment. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver.

● IOFF Supports partial-power-down mode operation

● Supports mixed-mode signal operation on all ports

● Latch-up performance exceeds 250mA per JESD 17

● Inputs accept voltages to 5.5V

● 4.1ns at 3.3V Propagation delay (tpd)

● <0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)

● >2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)

● Green product and no Sb/Br