SN75LVDS386DGG Datasheet PDF - TI

●DESCRIPTION

●This family of four-, eight-, or sixteen-, differential line receivers (with optional integrated termination) im

●plements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique

●lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the

●power, increase the switching speeds, and allow operation with a 3-V supply rail.

●FEATURES

●• Four- ("390), Eight- ("388A), or Sixteen- ("386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard

●• Integrated 110-Ω Line Termination Resistors on LVDT Products

●• Designed for Signaling Rates(1) Up To 630 Mbps

●• SN65 Version"s Bus-Terminal ESD Exceeds 15 kV

●• Operates From a Single 3.3-V Supply

●• Typical Propagation Delay Time of 2.6 ns

●• Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns

●• LVTTL Levels Are 5-V Tolerant

●• Open-Circuit Fail Safe

●• Flow-Through Pinout

●• Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch