●The SN75LVDS82DGG is a FlatLink™ Receiver contains four serial-in, 7-bit parallel-out shift registers, a 7x clock synthesizer and five low-voltage differential signalling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, over five balanced-pair conductors and expansion to 28-bit of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or SN75LVDS85 for 21-bit transfers. When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7x) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop (PLL) clock synthesizer circuit generates a 7x clock for internal clocking and an output clock for the expanded data. It presents valid data on the falling edge of the output clock (CLKOUT).
● 4:28 Data channel expansion at up to 238Mbps throughput
● Suited for SVGA, XGA or SXGA display data transmission from controller to display with very low EMI
● 4 Data channels & clock low-voltage diff channels in & 28 data & clock low-voltage TTL channels out
● Operates from a single 3.3V supply with 250mW
● 5V Tolerant SHTDN(bar) input
● Falling clock-edge-triggered outputs
● Consumes less than 1mW when disabled
● No external components required for PLL
● Inputs meet or exceed the requirements of ANSI EIA/TIA-644 standard
● Improved replacement for the National™ DS90C582
Part 3D Model
