LAN91C111 Datasheet PDF

●The LAN91C111I-NU is a 10/100 Non-PCI Ethernet single-chip MAC and PHY designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. It is a mixed signal analog/digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32, 16 or 8-bit bus Host interface in embedded applications. The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations. It is software compatible with the LAN9000 family of products. Memory management is handled using a patented optimized MMU (Memory Management Unit) architecture and a 32-bit wide internal data path.

● Fully supports full duplex switched Ethernet

● Supports burst data transfer 8kbyte Internal memory for receive and transmit FIFO buffers

● Enhanced power management

● Built-in transparent arbitration for slave sequential access architecture

● Flat MMU architecture with symmetric transmit and receive structures and queues

● Low power CMOS design

● MII Management serial interface

● Adaptive equalizer

● Baseline wander correction