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LAN91C111 Datasheet PDF

Part Series:
LAN91C111 Series
Category:
Interface ICs
Description:
Ethernet Controller, 100Mbps, IEEE 802.3, IEEE 802.3u, 2.97V, 3.63V, TQFP, 128Pins
Updated Time: 2023/01/13 02:38:47 (UTC + 8)

LAN91C111 Datasheet PDF Interface ICs

134 Pages
Microchip
Ethernet Controller, 100Mbps, IEEE 802.3, IEEE 802.3u, 2.97V, 3.63V, TQFP, 128Pins
134 Pages
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2Channel(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128, 14 X 14MM, 1MM HEIGHT, ROHS COMPLIANT, TQFP-128
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Ethernet Controller, 100Mbps, IEEE 802.3, IEEE 802.3u, 2.97V, 3.63V, QFP, 128Pins
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Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 128Pin PQFP
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Microchip
Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 128Pin TQFP
133 Pages
SMC
Microchip LAN91C111I-NU, Ethernet Controller, 10Mbps, 100Mbps MII, EISA, ISA, 3.3V, 128Pin TQFP
133 Pages
SMC
Ethernet ICs Non-PCI 10/100 Ethernet MAC
133 Pages
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Microchip LAN91C111-NU, Ethernet Controller, 10Mbps, 100Mbps MII, EISA, ISA, 3.3V, 128Pin TQFP
133 Pages
SMC
Ethernet ICs Non-PCI 10/100 Ethernet MAC

LAN91C111I-NU - Microchip Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Number of Pins
128 Pin
Supply Voltage (DC)
2.97V (min)
Case/Package
TQFP-128
Supply Current
100 mA
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LAN91C111I-NU - Microchip Function Overview

The LAN91C111I-NU is a 10/100 Non-PCI Ethernet single-chip MAC and PHY designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. It is a mixed signal analog/digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32, 16 or 8-bit bus Host interface in embedded applications. The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations. It is software compatible with the LAN9000 family of products. Memory management is handled using a patented optimized MMU (Memory Management Unit) architecture and a 32-bit wide internal data path.
Fully supports full duplex switched Ethernet
Supports burst data transfer 8kbyte Internal memory for receive and transmit FIFO buffers
Enhanced power management
Built-in transparent arbitration for slave sequential access architecture
Flat MMU architecture with symmetric transmit and receive structures and queues
Low power CMOS design
MII Management serial interface
Adaptive equalizer
Baseline wander correction
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