PC28F128 Datasheet PDF

●The PC28F128G18FE is a 128MB StrataFlash Embedded Memory featuring flexible, multiple-partition, dual-operation architecture. The device provides high-performance, asynchronous read mode and synchronous-burst read mode using 1.8V low-voltage, multilevel cell (MLC) technology. The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows two processors to interleave code operations while PROGRAM and ERASE operations take place in the background. The multiple partitions allow flexibility for system designers to choose the size of the code and data segments. This device provides high read and write performance at low voltage on a 16-bit data bus. The multi-partition architecture provides read-while-write and read-while-erase capability, with individually erasable memory blocks sized for optimum code and data storage.

● High-performance read, program and erase

● 96ns Initial read access

● Programmable WAIT configuration

● Customer-configurable output driver impedance

● Block erase - 0.9s per block typical

● 20µs Typical program/erase suspend

● Symmetrically-blocked array architecture

● Status register for partition/device status

● Blank check

● Minimum 100000 erase cycles per block

● Micron® Flash data integrator (FDI) optimized

● Basic command set (BCS) and extended command set (ECS) compatible

● Common flash interface (CFI) capable

● Power-transition erase/program lockout

● Individual zero latency block locking

● Individual block lock-down

● Address-data multiplexed and non-multiplexed interfaces