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TMS320C6711 Datasheet PDF

Part Series:
TMS320C6711 Series
Category:
Digital Signal Processors(DSPs)
Description:
DSP Floating-Point 32Bit 200MHz 1600MIPS 272Pin BGA
Updated Time: 2023/01/13 03:20:21 (UTC + 8)

TMS320C6711 Datasheet PDF Digital Signal Processors(DSPs)

109 Pages
TI
DSP Floating-Point 32Bit 200MHz 1600MIPS 272Pin BGA
109 Pages
TI
DSP Floating-Point 32Bit 250MHz 2000MIPS 272Pin BGA
109 Pages
TI
DSP Floating-Point 32Bit 200MHz 1600MIPS 272Pin BGA
109 Pages
TI
DSP Floating-Point 32Bit 250MHz 2000MIPS 272Pin BGA
109 Pages
TI
FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6711DGDP200 - TI Specifications

TYPE
DESCRIPTION
Mounting Style
Surface Mount
Frequency
200 MHz
Number of Pins
272 Pin
Supply Voltage (DC)
1.14V (min)
Case/Package
BGA-272
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TMS320C6711DGDP200 - TI Function Overview

description
The TMS320C67x DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D devices†) compose the floating-point DSP family in the TMS320C6000 DSP platform. The C6711, C6711B, C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.
• Excellent-Price/Performance Floating-Point Digital Signal Processor (DSP): TMS320C6711D
   − Eight 32-Bit Instructions/Cycle
   − 167-, 200-, 250-MHz Clock Rates
   − 6-, 5-, 4-ns Instruction Cycle Time
   − 1000, 1200, 1500 MFLOPS
• Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core
   − Eight Highly Independent Functional Units:
   − Four ALUs (Floating- and Fixed-Point)
   − Two ALUs (Fixed-Point)
   − Two Multipliers (Floating- and Fixed-Point)
   − Load-Store Architecture With 32 32-Bit
      General-Purpose Registers
   − Instruction Packing Reduces Code Size
   − All Instructions Conditional
• Instruction Set Features
   − Hardware Support for IEEE
      Single-Precision and Double-Precision Instructions
   − Byte-Addressable (8-, 16-, 32-Bit Data)
   − 8-Bit Overflow Protection
   − Saturation
   − Bit-Field Extract, Set, Clear
   − Bit-Counting
   − Normalization
• L1/L2 Memory Architecture
   − 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
   − 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
   − 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
• Device Configuration
   − Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
   − Endianness: Little Endian, Big Endian
• Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
• 32-Bit External Memory Interface (EMIF)
   − Glueless Interface to Asynchronous Memories: SRAM and EPROM
   − Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
   − 256M-Byte Total Addressable External Memory Space
• 16-Bit Host-Port Interface (HPI)
• Two Multichannel Buffered Serial Ports (McBSPs)
   − Direct Interface to T1/E1, MVIP, SCSA Framers
   − ST-Bus-Switching Compatible
   − Up to 256 Channels Each
   − AC97-Compatible
   − Serial-Peripheral-Interface (SPI) Compatible (Motorola)
• Two 32-Bit General-Purpose Timers
• Flexible Software Configurable PLL-Based Clock Generator Module
• A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
• IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
• 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffixes)
• CMOS Technology
   − 0.13-µm/6-Level Copper Metal Process
• 3.3-V I/O, 1.4-V Internal (−250)
• 3.3-V I/O, 1.20-V Internal ‡
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