EP1C12Q240C8N Datasheet PDF - Altera

●The EP1C12Q240C8N is a Cyclone® FPGA based on a 1.5V, 0.13µm features all-layer copper SRAM process with densities up to 12060 logic elements (LEs) and up to 239616-bit of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640Mbps and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices. It contains a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.

● Supports configuration through low-cost serial configuration device

● Supports for LVTTL, LVCMOS, SSTL-2 and SSTL-3 I/O standards

● Supports for 66- and 33-MHz, 64- and 32-bit PCI standard

● High-speed (640Mbps) LVDS I/O support

● Low-speed (311Mbps) LVDS I/O support

● 311Mbps RSDS I/O support

● Up to two PLLs per device provide clock multiplication and phase shifting

● Up to eight global clock lines with six clock resources available per logic array block (LAB) row

● Supports for external memory, including DDR SDRAM, FCRAM and single data rate SDRAM

● Supports for multiple intellectual property (IP) cores